1. Field of the Invention
The present invention relates generally to semiconductor packages having an electrical connection mechanism having carbon nanotubes and methods of manufacturing the same. The present invention relates more particularly to a semiconductor package having a connection mechanism that establishes an electrical connection through the contact of carbon nanotubes with a conductor or the contact of carbon nanotubes with each other and allows repeated detachment and (re-)attachment without damage, and to a method of manufacturing the same.
2. Description of the Related Art
The carbon nanotube is a fine conductor having a two-dimensional shape. It has been proposed to use a carbon nanotube for a vertical interconnect between circuit layers, taking advantage of its characteristic of high current density. (See, for example, Patent Document 1 and Patent Document 2.)
Further, since the carbon nanotube is formed of firmly bound carbon atoms, the carbon nanotube has the merit of extremely high mechanical strength. For example, it has been reported that the carbon nanotube sustains 1500 tons per cross-sectional area of 1 cm2. This means that the carbon nanotube can sustain 10 or more times as much force with the same cross-sectional area and a hundred or more times as much force with the same weight as steel wire.
On the other hand, the carbon nanotube has not only high mechanical strength but also flexibility and moderate elasticity. Accordingly, the carbon nanotube can also be bent flexibly without causing damage to its structure. Further, the carbon nanotube is a new material having merits such as high thermal conductivity.
It is known that the carbon nanotube can be formed by various methods. For example, it has been reported that it is possible to cause a carbon nanotube to be oriented and grow in a substantially perpendicular direction from a catalyst metal pattern selectively positioned and formed by CVD (Nihei, M.; Extended Abstracts of the 2003 International Conference on Solid state Devices and Materials, 798-799 (2003)).
In these years, multifunctional and small-size semiconductor devices have been developed at a rapid pace in response to demands for high-speed communications and large-capacity communications. At present, semiconductor packages have pin pitches less than or equal to approximately 50 μm. It is expected that the number of pins will increase so as to further reduce the pin pitch in the future as semiconductor packages become more multifunctional and smaller in size. It is known that as the pin pitch becomes smaller, a pin should be finer (thinner) because of dimensional restrictions so as to be reduced in its mechanical strength. Further, such an extra-fine pin has a disadvantage in that it can only be removed by cutting once connected by solder bonding.
Further, methods of vertically stacking and connecting multiple semiconductor chips have drawn attention as next-generation techniques of connecting semiconductor chips. These methods have the merit of being able to reduce an interconnection distance by vertically stacking and electrically connecting multiple semiconductor chips and accordingly to increase operating speed.
However, according to these methods, when one of the multiple chips fails, it is necessary to remove all the chips. Accordingly, these methods have a disadvantage in that not only the failed chip but also the other normal chips have to be destroyed at the time of their removal.
[Patent Document 1] Japanese Laid-Open Patent Application No. 2002-141633
[Patent Document 2] Japanese Laid-Open Patent Application No. 2002-329723